Low resistivity metals like copper and low permittivity (low-k) dielectric materials are widely used in IC manufacture to improve a circuit's performance. FIG. 1 of the above-referenced patent application illustrates the major steps of forming copper interconnects in a layer of low-k dielectric material (e.g., SiOC-based) which is on top of the surface of a semiconductor substrate. One of the steps is chemical-mechanical planarization (CMP), a process using an abrasive, corrosive slurry to planarize the surface of the copper interconnnects and the dielectric layer. The copper interconnnects left in the trenches in the dielectric layer are responsible for transmitting signals into and out of the circuit.
Due to the difference in hardness between the dielectric material and copper, CMP often causes a dishing effect on the top surface of a copper interconnect in which the top surface becomes concave. Moreover, two copper interconnects having same or the similar dimensional parameters (e.g., width and thickness) may have significantly different dishing effects and therefore different cross-sectional areas depending upon their respective locations and surrounding environments in the dielectric layer. This variation in cross-sectional area may lead to a variation in sheet resistance and parasitic capacitance from one interconnect to another, which may have an adverse impact on the performance of the circuit.
FIGS. 1(a) and 1(b) are a cross-sectional view and a top view of a structure in which the uniformity of dishing effect is improved by inserting metal regions between interconnect metal lines in different dielectric layers that are stacked on a semiconductor substrate. Following the practice in the art, these regions will be referred hereinafter as “dummy metals”. The cross-sectional view depicts three dielectric layers A, B and C stacked one on top of the other above a semiconductor substrate (not shown), each layer having multiple interconnect metal lines such as ground (“Gnd”) and signal (“Sgn”) lines. To reduce the variation in dishing effect, multiple dummy metals identified as FIGS. 1(a) and 1(b) as “Dummy” are filled into the dielectric layers, such that each dielectric layer has a substantially uniform metal density. Because each layer has substantially uniform metal density, different interconnect metal lines have similar cross-sectional areas and therefore similar sheet resistances after CMP. The top view of layer B illustrates this uniform metal density within layer B after filling the dummy metals.
Unfortunately, there is a side effect associated with the insertion of dummy metals in the dielectric layers. Referring again to FIG. 1, the inter-layer distance S1 between an interconnect metal line and a dummy metal is small due to the presence of dummy metals in the dielectric layers. This small inter-layer distance causes a significant amount of parasitic capacitance in the circuit, which may seriously limit the performance of the circuit. In view of the discussions above, there is a need to reduce the parasitic capacitance caused by dummy metals in the dielectric layers.